As a mask ROM of large capacity, there has been widely used such a NOR type mask ROM that the sources and the drains of memory cells are formed by N conductive type diffusion layers and the word lines are arranged perpendicular to the N conductive type diffusion layers.
FIG. 1 shows a circuit configuration of a memory cell array of a mask ROM, and FIG. 2 is a plan view of the same memory cell array.
In FIG. 1, the vertical bit lines 101 are formed by an N conductive type diffusion layer, and the horizontal word lines 102 are formed by a polyside. The NOR type bit lines 101 and the word lines 102 are arranged so as to intersect each other. The memory cell transistors 103 are formed in such a way that the source and drain regions are formed at the intersection portions, and the channels are formed between the intersection portions. The memory cell transistors 103 are manufactured by a technique of adjusting the impurity diffusion quantity of the channels. Each memory cell transistor 103 is formed to be turned on or off on the basis of a predetermined gate voltage according to whether an information bit is to be held by the cell. In the flat cells of the structure described above, since the N conductive type diffusion layers are used as bit lines, the resistance and the junction capacity of the bit lines inevitably become large. Accordingly, a block select structure is adopted to reduce the resistance and capacitance; that is, to realize a high speed reading operation. In the memory cell array shown in FIG. 1, only an i-th block is shown. Each block group is composed of 16 units of memory cells having even column select transistors 104 and odd column select transistors 105 both connected on both the ends of the bit lines 101 within each block, and 16 word lines WL.sub.0 to WL.sub.15 are connected as the respective gate electrodes thereof. The memory cell array is divided into 256 blocks in the direction of the bit lines 101. The respective bit lines 101 are connected to a main bit line 106 (formed of aluminum) via the even column select transistors 104 and the odd column select transistors 105. The lower end of the main bit line 106 is connected to a sense amplifier 114 via a column select transistor 113 controlled by a column select line CS. A virtual ground line 107 (also formed of aluminum) is connected to the source of the memory cell transistors 103 via the even column select transistors 104 and the odd column select transistors 105. The lower end of the virtual ground line 107 is grounded via a virtual ground select transistor 115 controlled by both the column select transistor 113 and a virtual ground select line VS. The main bit line 106 and the virtual ground line 107 are arranged adjacent to each other. Each of the memory cells belongs either to the even column 108 or the odd column 109. Therefore, it is possible to select any even column 108 or the odd column 109 by switching the even column select transistors 104 and the odd column select transistors 105 arranged on both ends of the bit lines 101.
To read data on the even column, when the even column select line 110 and a word line (e.g., WL.sub.15) are selected, for instance, these lines are changed to a high level (referred to as the "H" level), so that the even column select transistor 104 is turned on. Therefore, the source and the drain of the memory cell transistor 103' are connected to the aluminum virtual ground line 107 and the main bit line 106, respectively. Under these conditions, the odd column select line 111 is at a low level (referred to as the "L" level), so that the odd column select transistors 105 are kept off. Although the gate of the odd column memory cell 103" is also set to the "H" level via the word line WL.sub.15, since the sources and the drains of the odd column memory cells are shorted by the turned-on even column select transistors 104, the memory cell transistor 103" is kept off.
Successively, the column select line changes to the "H" level, and the virtual ground select line VS changes to the "H" level, so that the virtual ground line 107 is grounded in potential. Therefore, the main bit line 106 is connected to the sense amplifier 114.
Accordingly, when the even column select line 110 of the i-th block and the word line WL.sub.15 are selected, the value stored in the memory cell transistor 103' can be read by a sense amplifier 114 according to the presence or absence of the current flowing through the memory cell transistor 103'. The values stored in the memory cells arranged on the odd column can be read in the same way as above.
In the memory structure as described above, however, the current required to read data flows along the U-shaped route (the memory cell is at the base thereof). For instance, when the memory cell transistor 103' arranged on the even column is required to be accessed, current flows from a contact hole 112 to the even column select transistor 104 and further passing through both ends of the bit line 101 of a large resistance of the N conductive type diffusion layer. If the length of the bit line 101 of the N conductive type diffusion layer is l in the row direction thereof, the current flows through the N concductive type diffusion layer as long as a length of 2l at the worst. Therefore, a high voltage drop develops across the N conductive type diffusion layer, so that the number of word lines to be arranged within a single block is limited. In addition, since the voltage drop value differs according to the physical position of the selected memory cell, there exists a problem in that the margin (allowable range) of the sense amplifier is inevitably reduced.